Browsing by Author "Arem Chenna, Keshav Reddy"

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    An Efficient High Speed Wallace Tree Multiplier
    (2016-07-12T11:18:00Z) Adithya, Reddy M V; Arem Chenna, Keshav Reddy; Dinesh, M K
    Wallace Tree Multiplication Algorithm has been implemented in four different ways to design an 8x8 multiplier viz., 1) Using 7:3 and 5:3 compressors 2) Using Dual-Weight 5:3 compressors 3) Using Full-adders and Half-adders 4) Using 5:3 compressors designed using two cascaded full adders. All the above mentioned multiplier circuits are compared with an 8x8 Braun Multiplier circuit. The performance of all the circuits has been analysed and compared using Cadence Encounter tool.