Browsing by Author "PRIYANKA MILTON"

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    DESIGN AND IMPLEMENTATION OF 16*16 MULTIPLIER USING VEDIC MATHEMATICS
    (2019-06-14T07:19:37Z) PRIYANKA MILTON; PAVANA M; LAVANYA C Y
    This project describes the Urdhva-Tiryagbhyam Sutra of vedic mathematics and we have designed multiplier based on this sutra. Vedic Mathematics was described by Sri Bharti and it is an ancient method of mathematics which has a unique technique of calculations based on 16 Sutras which are discovered by Sri Bharti Krishna Tirthaji. In this era , it is required to increase the speed of the digital circuits so that reduces the on chip area and memory consumption. Most of the digital signal processing application, multiplication is one of the key component. Vedic technique of calculation eliminates the unwanted multiplication steps thus reduces the propagation delay in processor this in turn reduces the hardware complexity in terms of area and memory requirement. We excute the basic building block: 16 × 16 Vedic multiplier based on Urdhva-Tiryagbhyam Sutra. This Vedic multiplier is coded using VHDL and synthesized and simulated by using Xilinx ISE 10.1. Next the design of array multiplier in VHDL is compared with proposed multiplier in terms of speed and memory.