(2017-08-11T08:03:11Z) Mahesh Kumar, E V; Kushal Kumar, S V; Madhu, V
In this paper 8 bit SAR ADC with input voltage of 1.8V has been designed. The schematic diagram of
different sub blocks has been implemented in Cadence Virtuoso using 180nm technology. The
comparator is the main power consuming block, here Dynamic latched Comparator is used it is designed
in such a way that it consumes less power . so most of our effort was focused on designing this block. In
order to increase the precision, the R-2R ladder network was used for implementing DAC sub block. For
driving ADC, asynchronous control logic was designed using analog design.