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Item Verification of Ram Using System Verilog Architecture(2016-07-14T06:46:18Z) Venkatesh, DegoudImproving the functional coverage efficiency created on random constrained simulation in a verification environment is a challenging task. Certain designs are hard to be touched by making use of the random input patterns. Direct test patterns created manually is more time consuming. The verification plays an important role in confirming the design and functionality. In this paper, we are verifying the single port RAM real world design by using the System verilog verification environment. We propose a Functional Test Pattern Generator (FTPG) framework to generate the automatic deterministic test cases for the complete coverage model which are covergroups delivered by the System Verilog and this is integrated to the recent digital design flow. Here, we synthesize the real-world subset of covergroup language to enable the FTPG by the SAT-solver model. The input constraints, target coverage points are covered by the SAT-solver model and it recursively produce test patterns until all the coverage points are solved.Item 32 Bit Mac Unit Design Using 45nm Vedic Multiplier and Reversible Logic Gates(2016-07-14T06:40:40Z) Prathik, VMultiply and accumulate is a popular radical-level operation. Multiplication of two numbers in proximity, and adding these numbers to the accumulator. Any radical multiply and accumulate unit will involve a multiplier, one adder followed by an accumulator. To better the speed of the MAC unit we have the fractional products cut-down circuit implemented in the product generation unit and another is the accumulator enhancement. In any design the basic ideology will be to reduce power, area and delay similarly in my design optimization of the multiplier is of major importance. To optimize the multiplier design we should either reduce the amount of partial products generated, reduce the partial product addition term or optimize the final conventional addition methodology.one of the measures for this is use of Vedic multiplier ‘Urdhava-Tiryagbhyam’ along with Kogge stone adder, the fastest adder known till date in my design. Reverse technique is a unique method where Loss of information is not possible. The outputs circuit parameters are equal to the input circuit parameters. DKG gate that can be used as an adder for the MAC unit is implemented. The design of 32 bit multiply and accumulate unit making use of 45nm technology node design Vedic multiplier and reversible logic function has two parts as follows. Digital circuit generated by writing a Verilog code and the analog design in 45nm. Simulation and synthesis is carried out using Cadence tools, Simvision tool to perform simulation and Encounter tool to perform synthesis. Analog design is done by importing Verilog netlist from Encounter to Virtuoso and generate a schematic. Later designing the smaller modules like the basic gates manually and linking them to generated schematic. Results show that the design is optimized. A comparative study of previous architectures of adders and multipliers is done and found that the results obtained are better in all aspects. The design has vast application mainly in digital signal processing and communication, almost every digital signal processor requires a MAC unit. Additional applications of a MAC unit could be in instrumentation engineering, image processing and many more. As a part of future scope the complete design has high room for evolution. Implementation of 45nm technology can further come down depending upon the technology node used and design standard. The MAC unit bit weight can be enhanced from 32 to higher 64,128.Depending upon the application. Adders if improved the speed off multiplication can be improved with upcoming technologies and hence further optimize the MAC design.Item Implementation Of DCT Architecture Using Low Power Mixed Signal Design(2016-07-13T11:23:41Z) Sunarthy, NIn real time DSP algorithms face the restrictions towards the accuracy factor, speed limitations and round off noise etc., in case it is implemented with digital circuits. Analog circuits are preferred to offer effective designing with mixed signal design. As it eliminates certain restrictions contained in Digital circuits. With this work based on sampled analog designing offers several fruitful results in case of real time signal processing . Here the signal processing is done in analog array domain in order to eliminate the use of digital to analog converter and also eliminates analog to digital converter and with this concept DSP algorithms will be possible to implement. This is mainly due to discrete nature of the data being processed. In the case of DSP algorithms multiply and accumulation function is the most important function. Further in the work presented here is about the architecture for computation of DCT which relies on the switched capacitor to implement the MAC function in the mixed signal design or analog domain. To enhance and cope with error factor and accuracy we have started with capacitor and switch, to have the multiply operation. In case of SC circuit based multiplier, potential distribution obtained by charge sharing of capacitors due to discharging and charging logic of capacitors , this is done by the help switches. Once the multiplication is over the accumulation process will be carried out by the integrators. With respect to the clocks we can have the integrator realized for both modes of inverting and non-inverting. Also various NOC generator and respective jitter noise associated with is discussed. These discussed methodologies are tested with appropriate simulation with commercially available 250 nm technology. The obtained simulated result will point out how much suitable it is to the discussed architectures for several applications that needs different accuracy and speed. The limitations of digital circuits are minimized with these data architectures. On whole we have arrived at architectures which are simple in design and robust to implement and available. The great advantage is that this work can be extented to all those discrete linear transform and their inverses.Item Power Quality Mointoring Using Fft Method with FPGA Based Processing(2016-07-13T11:21:02Z) Vani, Parimala KPower Quality monitoring is very important especially for high frequency nonlinear loads, high speed adjustable drivers. As there is a tremendous development in electronics and telecommunication, nonlinear loads have been increased. Many devices are controlled by microprocessor based technology and these devices are more sensitive to electromagnetic disturbances caused by neighboring devices. This leads to instability and short life time of the equipment even some times the entire system may collapse. Hence, accurate measurement of electrical parameters is required to determine the quality of power which involves collecting, analyzing and processing of voltage and current samples over a period. So addressing to this we need power meter that measures electric parameters with high accuracy and computation speed. Though electromechanical power meter are of low cost but still they are replaced by electronic meters because of its accuracy and better dynamic range. In electronic meters, there are many existing meters implemented with microprocessor based for data processing but here FPGA based processing has been implemented as it provides more flexibility, speed and ability to update system functionality. The objective of the project is to provide a meter which measures electric parameters like real power, reactive power and power factor of different loads. This project is carried out using FPGA data processing; the meter includes ADS1220 which is 24 bit ADC interfacing with FPGA (Artix 7) which provides voltage and current digital samples. These samples are processed and FFT is implemented for power calculations. The analytical calculations and outputs generated in Xilinx ISE 14.7 version tool using VHDL language. For 50 Hz power system with sampling frequency 12.8 KHz 256 point FFT is implemented for power calculations. The system is tested on different loads like resistive load, 40 watt bulb with dimmed switch. Initially, the bulb is glowing with the power factor of unity and as the bulb is dimmed the meter showed increase in the reactive power and decrease in the power factor. The meter is also tested for industrial drill (inductive load).Item Digital Conversion Of Antenna Beam Forming Unit In Primary Radar Subsystem Using VHDL(2016-07-13T11:13:11Z) Nithin, Kumar N.R.Antenna beam forming unit is a digital beam forming unit in which the radar system is will be able to steer the RF signal in azimuth as well as in elevation which is done by variable attenuators and phase shifters which is controlled digitally through FPGA the radar will steer the beam in 0 to 300 degrees. Steering angle is depending upon antenna beam forming unit thus it is depending upon the phase shifting angles in the transmitter section. As the antenna beam forming unit is used in a military radar system a few thousands of antenna arrays are used for the accurate information of the target. In transmitter section the input RF signal is converted into different channels thus to each antenna. In the receiver section all the received echoes are combined and formed to get sum and difference signal. Difference signals gives rises to azimuth and elevation angle using mono pulse tracking method. The digital conversion referred to the control over the digital components like phase shifter, attenuator, two way switch for transmit and receive section, temperature sensor and threshold detector. Digital data is fed to the beam forming unit serially and then it is converted to parallel data and at each instance the phase shifter and attenuator values are updated. To store the digital data flash memory is used and to process it SD RAM is used. Thus antenna beam forming unit is used to steer the RF signals in different phase angles.Item Efficient Repair Technique For 3d-Stacked Dram (Off-Chip Access+Memory Mapping)(2016-07-13T11:01:51Z) Shashi, Kumar.GThree dimensional integration of memory die is one of the advantageous method to increase the efficiency and performance of large scale integrated computing circuits but the main drawback is with respect to the yield of the system. To address this challenge and enhance the yield of the system we have to develop a way to improve the yield of the system without affecting other parameters such as performance, area, efficiency and power consumption. One of the ways to achieve yield improvement is by using spares during redundancy repair. This is usually achieved by making small architectural modifications of DRAM memory design so as to provide off-chip access of the memory elements and performing operations such as address comparison to identify the faulty address location if present and address mapping to the spare address to achieve memory repairing. This additional architectural modification area overhead can be neglected when yield of the system is of main concern. Simulation results display that the additional area consumed for modification is very less and power consumption for the additional circuit is also less and timing penalties are under control when only yield of a system is of main concern.Item Experimental Analysis And Design Of 1-D Median Filter Architecture With Rank Selection And Generation Process For Low Power Consumption(2016-07-13T10:47:49Z) Arjun, Ayagiri TMThis brief is to design a low power median filter based on 2-stage pipelined architecture where, word-level sorting of samples are used in the architecture in which the samples are accepted sequentially in a FIFO manner and median output is generated at each machine cycle. Ring architecture is used in this design with the help of token registers to make the samples immobile to reduce the power consumptions. Performance of the filter is shown by reducing the number of LUTs in the Rank Selection Module in turn, where it reduces the delay, area, power consumption and increases the speed of operation. Signal range is improvised to transmit more data in less time by reducing the switching activities in the architecture by using the token registers in the ring format as adopted in the design. Evaluated simulation results are showed in the analysis and validated as per the design.Item Design And Implementation Of Estimation Algorithm And HDL Code Conversion(2016-07-13T10:43:49Z) Amruta, Shankarappa RadderThe accurate attitude estimation and use of Micro-Air Vehicle (MAVs) plays an increasing role in the military and civil realms and gradually lowers the limitations of mass and load and the newer technology made MAVs minuet and less pricey, they have become more easy to use and general in their roles. This paper considers targeting the High-end processor like FPGA for the implementation of state estimation which measures difficulty in a low end processor. To achieve the high performance and accuracy, FPGA is the best choice as it provides high flexibility of implementing mathematical function. Here the model based design approach HDL coder is preferred, which is best platform to generate portable VHDL code, to mechanically generate the HDL code from MATLAB script. A Non Complementary Filter (NCF) filter is proposed in this paper for the attitude estimation of yaw, pitch and roll from measurements obtained from typically low cost inertial measurement unit (IMU) which consists of 3-axis accelerometer, 3-axis rate gyros and 3-axis magnetometer. The NCF algorithm is fast and much efficient than a Kalman Filter (KF) algorithm it’s because the NCF does not involve any calculation of matrix inverses which is used in KF. The proposed NCF algorithm is implemented in the MATLAB software and the use of HDL coder will mechanically convert MATLAB code from floating to fixed point and generate synthesizable VHDL code.Item RFID And ZIGBEE Based Intelligent Traffic Control System(2016-07-13T10:39:12Z) Bhargavi, Yadav NThis project presents an intelligent traffic control system to ensure smooth flow of traffic. Vehicle is equipped with special Radio Frequency Identification (RFID) tag, placed such that it is impossible to remove or destroy. RFID reads when a vehicle comes in the range, and counts the number of the vehicles on a particular path for a specified duration and determines the congestion and hence the green light duration. If the RFID-tag-read belongs to the stolen vehicle, immediately a message is sent along with the latitude and longitude details to the police control room using GSM SIM300 module and GPS. Also, the traffic signal is turned to red making the vehicle to stop at the traffic junction. In addition, when an ambulance with an emergency case approaches the junction, it communicates wirelessly with the traffic controller using ZigBee modules to turn ON the green light.Item Analysis of ECT Using Parallel VLSI Architectur(2016-07-13T10:11:06Z) LavanyaThis paper presents a architecture for real time electrical capacitance analysis using VLSI. It consists of front end module which gives accurate capacitance value in time multiplexed manner using capacitance to digital converter technique. The architecture consists of dual port built in memory banks to save the sensitivity matrix, accurate capacitance value and the image. It is used to reduce the quantization errors of the image in order to improve the image quality. To check the preciseness bit level simulation is used. The recommended architecture is used to increase the speed of the system three times than the previous version. It uses the combination of linear back projection, landweber and modified landweber algorithms to improve the throughput. Image reconstruction is the main task involved in analysis of ECT. The algorithms mentioned are used to reconstruct the image with good accuracy. The proposed system is used to reconstruct the image of RGB colour pixels with better speed andaccuracy.ECT finds the main application in process tomography to measure the density of the flows inside vessel or closed pipes.Item Design And Implementation Of Ethernet Based Analyzer For Avionics Serial Bus On FPGA(2016-07-13T09:58:03Z) Tamrakar, IshaItem Design And Implementation Of Live Tap For Deterministic Ethernet Bus Using FPGA(2016-07-13T09:46:25Z) Jyothi, GEthernet emerged as the most preferred local area network standard for the microcomputers based environment in 1980. The different Ethernet LAN implementations are specified in IEEE 802.3 standards which operates at 10 Mbps over coaxial cable, 100- Mbps Ethernet that operates over twisted pair cable, 1000-Mbps Ethernet also known as Gigabit Ethernet which operates over fiber optic cable and also on twisted pair cables. Ethernet uses a control method called Carrier Sense Multiple Access/Collision Detection (CSMA/CD). It determines how the devices respond when two devices using the same cable simultaneously. It also determines the collision between the packets. A Live or Network TAP is a device which provides a way how to access and monitor the data flowing across an Ethernet link when two stations transmitting and receiving simultaneously. With the availability of the accurate live Ethernet monitoring tool having high accuracy is required for the analysis and test the Ethernet line. The timing analysis of the Ethernet packets is important in the avionics application to characterize the frame transmission and reception. The packet analysis should be done without disturbing the Ethernet communication system. This finds application in real time communication applications like avionics systems. Data communication between avionics system through Ethernet based communication demands critical analysis for characterization and analysis of Ethernet packets. The current project is “Design and Development of Ethernet based live tap for deterministic Ethernet bus using FPGA”. This project includes design, development, and integration, testing of FPGA based design for Ethernet line packet monitoring system using network TAPs along with the communication to the host for visualization. The project shall be implemented on Spartan 6 based SP605 FPGA board. The capture and analysis of the packet shall be done for packets transmitted in both directions.Item HDL Code Conversion and Implementation of the Flight Control Algorithm(2016-07-13T07:30:25Z) Anusha, Kumari A CMicro Aerial Vehicle is a kind of Unmanned Aerial Vehicle it has a size limit with flying in manual or autonomous mode. Advanced aircraft has a size of about as small as fifteen centimeter. Improvement is determined by the commercial research administration and military resolves with an insect-sized aircraft expected in the future. Autopilot system is the brain of the aircraft that control all the functionality in the autopilot mode. This system takes care of flight planning and control of the aircraft without manual interface. During the flight of MAV, many parameters like pressure, temperature, location, direction, gas, velocity, voltages and currents have to be monitored. The data from the sensors are to be saved into a SD card and has to send to the ground station for monitoring the condition to ensure that it accomplishes the assigned mission. The primary objective of this project is to control different parts of the flight control system such as ailerons, elevator, rudder flaps and propeller. Servos are used to control these surfaces for maneuvering the aircraft. These servos are controlled by signal generated from the autopilot system using on the attitude and flight control algorithm. These algorithms are designed in the MATLAB environment using script (.m file), Simulink block and State-flow. The MATLAB files can’t be used directly in the FPGA environment which requires the VHDL or Verilog coding. These files are converted in HDL languages and used to program the FPGA using appropriate tools like ISE/Vivado. This provides great flexibility in terms of writing the Flight Control Algorithm in the MATLAB as the same if written into HDL directly will take comparatively more time and modification is also a tedious task for the same. This project attempts to create a Model Based Design workflow using some part of Flight Control Algorithm and putting into the FPGA and testing of the algorithm functionality. Attempts will be made to use full flight control code once the workflow is established successfully.Item Experimental Evaluation of Consistent Path Loss Models over Mobile Network(2016-07-13T07:17:29Z) Gitanjali, KumariIn mobile network environment all the data transmissions purely depends on the quality of wireless channels. Each packet accuracy is dependent on the communication channels. Path loss is a major issue in every wireless mobile network situation. The former methodology path loss models are not much accurate, which requires excessive measurement or computational overhead, and/or cannot be made to signify a specified situation. The proposed framework contributes an adaptable way misfortune demonstrate that uses a novel methodology for spatially intelligible introduction from accessible adjacent channels to permit precise and effective demonstrating of way misfortune. We show that the proposed model, called Double Regression (DR), creates a interrelated space, sanctioning both the sender and the receiver to move without abrupt change in path loss. Joining DR with a transient fading model, for example, Rayleigh fading gives a precise and effective channel demonstrate that we coordinate with the NS-2 simulator. In the proposed approach we utilize the estimations to accept the precision model for various situations as well as additionally demonstrate that there is significant effect on reproduction behavior when losses in transmission is displayed precisely. Apart from the paper we improve the path consistency along with data security techniques such as AES and DES; we combine both these algorithms and form a proposed algorithm called Visual AES to make the data more secure while transmission.