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Item Design of Low Power Automatic Test Pattern Generator for Bits(2015-12-11T06:12:37Z) Mahantesh, I. M.Low power consumption has become increasingly important in hand-held communication systems and battery operated devices. For this new class of battery powered devices, energy consumption is the critical design issue since it determines the lifetime of batteries. Thereby the reduction of power consumption and the quality of the system should be tested are becoming one of the most growing topics of interest in industry. The proposed new low power test pattern generator is designed using a linear feedback shift register (LFSR), called LP-TPG, is presented to reduce the dynamic power consumption of a circuit during test. This is accomplished by reducing the number of bit transitions between the successive test patterns generated by LP-TPG which is contrast to the conventional LFSR. The goal of LP - TPG design is to reduce the transitional activities at the primary inputs which eventually reduce the switching activities inside the circuit under test, hence the power consumption and to achieve the desired fault coverage for Circuit under Test (CUT).Item Design & Synthesis of Low Power Speed Efficient VLSI Adder(2015-12-11T06:11:11Z) Madonna, Jennifer.TThe adding of two binary numbers is the basic arithmetic operation on microprocessors, digital signal processors. Parallel prefix adder is a general technique for speeding up binary addition. This method performs logic functions which determine whether groups of bits will generate or propagate a carry. In this project, a 32-bit kogge stone adder is one type of parallel prefix adder designed and synthesized. Kogge stone is the fastest adder. The 32-bit kogge stone adder is compared with adders of different bit width in terms of power, delay. Finally the performance improvement of the proposed adder is validated by designing FIR filters. The design entry is done in Verilog and simulated using Model- Sim SE 6.4 design suite from Mentor Graphics. For RTL compilation and synthesis Cadence design tools rc and Encounter is used.Item Design & Development of A High Speed ALU Using Vedic Maths for a Μc/Μp on Fpga(2015-12-11T06:10:06Z) Manjula, VThe design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Power is recognized as a critical parameter in modern VLSI design field. Multipliers have an important effect in designing arithmetic, signal and image processors. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors today, especially in the ALU design. Such a multiplier can be designed using Vedic mathematics. Vedic mathematics has a unique technique of calculations based on simple rules and principles with which any mathematical problem can be solved – be it arithmetic algebra, geometry or trigonometry. This project designs an energy efficient and high speed 8-bit Vedic ALU that performs various arithmetic operations such as addition, multiplication & addition and logic operations such as AND, NAND, OR, NOR, XOR, XNOR, etc. The traditionally used multiplier architecture are Booth and Modified Booth multipliers. These architectures involve iterative & time consuming operations and these iterations increase linearly as the number of bits to be multiplied increases. This leads to high power consumption and a significant decrease in speed. The Vedic ALU utilizes a multiplier architecture designed based on the Urdhva Tiryagbhyam sutra of Vedic mathematics. Due to factors of efficiency, speed and lesser area, the proposed Vedic multiplier can be implemented in Arithmetic and Logical Units replacing the traditional multipliers. A comparison of the proposed multiplier & conventional multipliers is done with respect to area, speed, & power. The ALU designs, embedding the conventional multipliers and the Vedic multiplier are also compared. The Vedic ALU designed is further modified to have a single unit that performs multiplication, addition and subtraction called the MAS structure, to compress the area utilized. This modified ALU structure can be used in any processor application. The project also involves a microcontroller module and a FIR filter design to show the effective application of the Modified ALU architecture. The ALU is implemented on Xilinx Spartan 3E FPGA.Item Hardware Implementation of AES Using Minimal Resources(2015-12-11T06:08:50Z) Neeraj, G NRapid development and wide application of computer and communication networks has aroused high attention in the information security. Information security is not only applied to the political, military and diplomatic fields, but also applied to the common fields of people’s daily lives. With the continuous development of cryptographic techniques, the long-serving DES algorithm with 56-bit key length has been broken because of the defect of short keys. The "Rijndael encryption algorithm" invented by Belgian cryptographers Joan Daemen and Vincent Rijmen's had been chosen as the standard AES (Advanced Encryption Standard) algorithm whose packet length is 128 bits and the key length is 128 bits, 192 bits, or 256 bits. Since 2006, the Rijndael algorithm of advanced encryption standard has become one of the most popular algorithms in symmetric key encryption. AES can resist various currently known attacks. Increasing need of data protection in computer networks led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. Hardware implementation of cryptographic algorithms are physically secure than software implementations since outside attackers cannot modify them. In order to achieve higher performance in today’s heavily loaded communication networks, hardware implementation is a wise choice in terms of better speed and reliability. This project presents the hardware implementation of Advanced Encryption Standard (AES) algorithm using Xilinx Field Programmable Gate Array (FPGA). In order to achieve higher speed and lesser area, Sub Byte operation, Inverse Sub Byte operation, Mix Column operation and Inverse Mix Column operations are designed as Look Up Tables (LUTs) and Read Only Memories (ROMs). Shift Row operation is designed in such a way that it does not take any hardware so it reduces chip area and save power.Item Implementation of Modified Architecture for Adaptive Viterbi Decoder(2015-12-11T06:07:40Z) Niranjan, D RIn digital communication systems, nowadays the transmitters convolutionally encode data to compensate for Additive White Gaussian Noise (AWGN), quantization distortions, and data degradations. The Viterbi decoder is identified as an efficient decoder to decode convolution codes in the receiver. The demand for high speed, low power and low cost for digital systems motivates the VLSI designer to have multiple different architectures for viterbi decoder. The project proposes the design of efficient algorithm for viterbi decoder to achieve fast processing of data in the decoder. Multiple different methodologies, logical blocks, architectures and algorithms are proposed for the design of Viterbi decoder to compensate for area, speed and power. The project uses one such algorithm which achieves fast processing of data in trace back unit. The trace back unit is one among the four main processing blocks of data in viterbi decoder. This new algorithm is called Adaptive Viterbi Decoder (AVD). An Adaptive Viterbi decoder contains four important data processing blocks, they are, Branch metric Unit (BMU), Add compare select unit (ACSU), Path metric unit (PMU), State metric unit (SMU). The trace back unit is considered as sub block of state metric unit and this is the key data processing block for the design of new algorithm called adaptive viterbi algorithm. An Adaptive Viterbi Decoder proposed here is able to operate at high clock speed as a result of reduction in the power and cost in trace back unit.Item Design and Analysis of Multiple Bit Pipeline ADC for Wireless Communication System(2015-12-11T06:06:30Z) Praveen, kumar JHigh-Performance analog to digital converters (ADC’s) are needed for applications in wireless telecommunications, medical imaging, audio and video processing. The pipeline topology is a popular option for wireless communication system which requires resolutions on the order of 8 to 14 bits and sampling rates between a few MS/s to hundreds of MS/s. The pipelined ADC is a multistep ADC. It consists of N stages connected in series. Each stage can be 1, 1.5, 2 or 3 bit. One interesting aspect of this converter is its dependency on the most significant stages for accuracy. A slight error in the first stage propagates through the converter and results in a much larger error at the end of the conversion. One of the disadvantages of the multiple – bit pipeline ADC that uses residue amplification is the bandwidth limitation of amplifier. It is difficult to implement standard operational amplifiers within high-resolution data converters because of these accuracy requirements. The non-ideal characteristics of the op-amp are well known and in many cases alone limit the accuracy of the data converter. The main goal of this work is to address the issues related to requirement of DC gain and gain bandwidth of residue amplifier, design consideration of sub-ADC, design consideration of sub-DAC and its impact on accuracy of pipeline ADC. The suitable techniques are identified and incorporated to solve the above issues. The multi-bit pipeline ADC is designed for a 10 bit resolution using CMOS 0.18um technology. The targeted Signal to Noise Ratio (SNR) would be around greater than 55 dB at the sampling rate of 100MSPS.Item Design of 16 X 16 Bit Multiprecision Multiplier Raghu(2015-12-11T06:04:53Z) Raghu, LMultiplication is the basic building block for several DSP processors, Image processing and many other. Over the years the computational complexities of algorithms used in Digital Signal Processors (DSPs) have gradually increased. Multiprecision multipliers reduce power consumption by selecting smaller multipliers (i.e. sub multiplier blocks) according to the size of the input operands. In this project, a Multiprecision (MP) multiplier that incorporates variable precision, parallel processing (PP), and dedicated MP operands scheduling to provide optimum performance for a variety of input operating conditions. All of the building blocks of the proposed multiplier can either work as independent smaller-precision multipliers or work in parallel to perform higher-precision multiplications. So, the internal components are designed in such a way that they should consume less power. To consume less power the transistor count should be reduced and obviously area will reduce. The high performance multiplexer based pass transistor low power full adder circuit is designed. By using this full adder MP multiplier sub blocks are designed. The MP multiplier unit works for different precision of input such as 8, 16, 8 x 16, 16 x 8, 16 x 16 bit, which reduces the power consumption and area. The unused blocks are removed when precision multiplication depending upon the inputs applied. Reuse of sub blocks of MP multiplier is advantage of designing. Finally, the proposed MP multiplier is designed using Verilog HDL in Cadence 180nm CMOS technology.Item LSB Steganography Method Implementation in FPGA Hardware(2015-12-11T06:03:10Z) Rajesh, LSteganography is one of the most powerful techniques to conceal the existence of hidden secret data inside a cover object. Images are the most popular cover objects for steganography, and thus the importance of image steganography. Embedding secret information inside images requires intensive computations, and therefore, designing steganography in hardware speeds up steganography. This work presents a hardware design of Least Significant Bit (LSB) steganography technique implemented on an FPGA. The design can used standalone or along with a soft-processor as a image processing peripheral. There are several techniques to conceal information inside cover-image. The spatial domain techniques manipulate the cover-image pixel bit values to embed the secret information. The secret bits are written directly to the cover image pixel bytes. Consequently, the spatial domain techniques are simple and easy to implement. The Least Significant Bit (LSB) is one of the main techniques in spatial domain image steganography. In this work we propose a new technique of steganography which is an improvised version of the regular one bit LSB technique and other techniques mentioned in the papers. This is 2-2-2-2 LSB steganography and we find that it is better in terms of image quality and also in terms of embedding message.Item Design and Implementation of Continuous-Time Sigma-Delta ADC Using 180nm CMOS Technology(2015-12-11T05:56:56Z) Sharath, Babu M GItem Devising and Developing of a Novel Segmentation Algorithm for Image Processing(2015-12-11T05:55:49Z) Soujanya, SDifferent diseases and bioagressor are affecting the crops, due to which the plants cannot survive for a long duration. Mainly the bioagressor which is been frequently seen on the leaves of the plant is the whitefly. The objective is to detect the number of whiteflies on the leaves. Different existing algorithms are used such as Otsu algorithm, watershed algorithm and k-mean clustering but these existing algorithms are not accurate and are slow in detecting the number of pest on the leaves. Hence a New Novel Segmentation algorithm is proposed which is highly accurate and high speed. The automatic early detection of pests on the leaf helps in deciding the amount of pesticides to be sprayed on the leaf. The results of both existing algorithms are compared with the New Novel Segmentation algorithm and its has been observed that New Novel Segmentation algorithm gives the greater accuracy.Item Design of Folding and Interpolating Flash ADC(2015-12-11T05:54:32Z) Steffi, LalIn recent advances ADC’s and DAC’s plays an important role in VLSI design. The low power consumption and less area are the important factors that demand in the trend. Flash ADC is the one of the faster way to convert the analogue signal to digital. When it comes for higher resolution the number of comparators increases which in turn increases the area and power consumption. In Very Large Scale Integrated circuit’s area and power consumption reduces the market value of the device. To reduce the area and power new techniques has to be implemented. One of the technique is Folding and Interpolating ADC. It will reduces the number of comparators in one ADC. For normal 8 bit Flash ADC 256 comparators are needed. In folding and interpolating ADC need only 39 comparators. The ADC is divided in to two. Coarse ADC of 3 bits. This produces the 3 MSB bits, and 5 bit fine ADC which produces 5 LSB bits.Item A Novel Architecture of High Speed Mac Using Radix-4 Modified Booth Algorithm(2015-12-11T05:45:28Z) Vittalprasad, B RThis project focused on a combined process of Multiplication and Accumulation based on Radix-4 Booth encodings. In this Project, I investigate the method of implementing the MAC with the smallest possible delay, where MAC is frequently used in digital signal processing and video/graphics applications. A new architecture of multiplier and accumulator (MAC) for high speed arithmetic is designed, by combining multiplication with accumulation and devising a hybrid type of carry save adder (CSA), the performance was improved. Since accumulation is also delay in MAC was merged into CSA, the overall performance was elevated. The new MAC provides high speed multiplication and multiplication with accumulative addition thus enhancing the speed of operation of the MAC, which is the major design issue. Modified Booth’s algorithm (MBA) has reduced partial products and has the modified array for the sign extension in order to increase the bit density of the partial products. The CSA propagates the carries to the least significant bits of the partial products and generates the least significant bits in advance to decrease the number of the input bits of the final adder. The Final adder used is CSLA with Common Boolean Logic, which is power and area efficient. Also, the proposed MAC accumulates half of the result, while remain higher half is given to final adder for addition which improves the overall performance of MAC. The proposed architecture is synthesized with Cadence digital tool.