Efficient Repair Technique For 3d-Stacked Dram (Off-Chip Access+Memory Mapping)
| dc.contributor.author | Shashi, Kumar.G | |
| dc.date.accessioned | 2016-07-13T11:01:51Z | |
| dc.date.available | 2016-07-13T11:01:51Z | |
| dc.date.issued | 2016-07-13T11:01:51Z | |
| dc.description.abstract | Three dimensional integration of memory die is one of the advantageous method to increase the efficiency and performance of large scale integrated computing circuits but the main drawback is with respect to the yield of the system. To address this challenge and enhance the yield of the system we have to develop a way to improve the yield of the system without affecting other parameters such as performance, area, efficiency and power consumption. One of the ways to achieve yield improvement is by using spares during redundancy repair. This is usually achieved by making small architectural modifications of DRAM memory design so as to provide off-chip access of the memory elements and performing operations such as address comparison to identify the faulty address location if present and address mapping to the spare address to achieve memory repairing. This additional architectural modification area overhead can be neglected when yield of the system is of main concern. Simulation results display that the additional area consumed for modification is very less and power consumption for the additional circuit is also less and timing penalties are under control when only yield of a system is of main concern. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/6231 | |
| dc.language.iso | en | en_US |
| dc.subject | Efficient Repair Technique For 3d-Stacked Dram (Off-Chip Access+Memory Mapping) | en_US |
| dc.subject | Shashi Kumar.G | en_US |
| dc.title | Efficient Repair Technique For 3d-Stacked Dram (Off-Chip Access+Memory Mapping) | en_US |
| dc.type | Thesis | en_US |