Design of Folding and Interpolating Flash ADC
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Date
2015-12-11T05:54:32Z
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In recent advances ADC’s and DAC’s plays an important role in VLSI design. The low power consumption and less area are the important factors that demand in the trend. Flash ADC is the one of the faster way to convert the analogue signal to digital. When it comes for higher resolution the number of comparators increases which in turn increases the area and power consumption. In Very Large Scale Integrated circuit’s area and power consumption reduces the market value of the device. To reduce the area and power new techniques has to be implemented. One of the technique is Folding and Interpolating ADC. It will reduces the number of comparators in one ADC. For normal 8 bit Flash ADC 256 comparators are needed. In folding and interpolating ADC need only 39 comparators. The ADC is divided in to two. Coarse ADC of 3 bits. This produces the 3 MSB bits, and 5 bit fine ADC which produces 5 LSB bits.
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Design of Folding and Interpolating Flash ADC, STEFFI LAL