Error Correction Capability using Reed Solomon Encoder / Decoder Algorithm and its implementation FPGA and ASIC Platforms
| dc.contributor.author | Kushal, .S | |
| dc.contributor.author | Kiran, .N | |
| dc.contributor.author | Detphung Gwra, Narzary | |
| dc.date.accessioned | 2015-12-22T07:04:55Z | |
| dc.date.available | 2015-12-22T07:04:55Z | |
| dc.date.issued | 2015-12-22T07:04:55Z | |
| dc.description.abstract | In coding theory, Reed–Solomon (RS) codes are non-binary cyclic error-correcting codes invented by Irving S. Reed and Gustave Solomon. They described a systematic way of building codes that could detect and correct multiple random symbol errors. By adding t check symbols to the data, an RS code can detect any combination of up to t erroneous symbols, and correct up to [t/2] symbols. As an erasure code, it can correct up to t known erasures, or it can detect and correct combinations of errors and erasures. Furthermore, RS codes are suitable as multiple-burst biterror correcting codes, since a sequence of b+1 consecutive bit errors can affect at most two symbols of size b. The choice of t is up to the designer of the code, and may be selected within wide limits. In Reed-Solomon coding, source symbols are viewed as coefficients of a polynomial P(x) over a finite field. The original idea was to create n code symbols from k source symbols by oversampling P(x) at n > k distinct points, transmit the sampled points, and use interpolation techniques at the receiver to recover the original message. That is not how RS codes are used today. Instead, RS codes are viewed as cyclic BCH codes, where encoding symbols are derived from the coefficients of a polynomial constructed by multiplying P(x) with a cyclic generator polynomial. This gives rise to an efficient decoding algorithm, which was discovered by Elwyn Berlekamp and James Massey, and is known as the Berlekamp - Massey decoding algorithm. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/5439 | |
| dc.language.iso | en | en_US |
| dc.subject | Error Correction Capability using Reed Solomon Encoder / Decoder Algorithm and its implementation FPGA and ASIC Platforms | en_US |
| dc.subject | Kushal .S | en_US |
| dc.subject | Kiran .N | en_US |
| dc.subject | Detphung Gwra Narzary | en_US |
| dc.title | Error Correction Capability using Reed Solomon Encoder / Decoder Algorithm and its implementation FPGA and ASIC Platforms | en_US |
| dc.type | Thesis | en_US |