Design and Implementation of Low Power PLL in 0.18 CMOS Technology Using Custom Design Approach
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Date
2016-08-23T10:40:15Z
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Abstract
Contemporary digital systems use clocks for sequencing their operations and for
synchronizing between different functional units. Phase locked-loops (PLLs) are widely used
in order to generate well-timed on-chip clocks to be used in high-performance digital
systems. A PLL is a closed loop system that locks the phase of its output signal to an input
reference signal. PLLs are widely used in radio, computer and telecommunications systems
where it is necessary to stabilize a generated signal or to detect incoming signals. PLL is a
simple negative feedback architecture that allows economic multiplication of crystal
frequencies by large variable numbers. By studying the loop components and their reaction to
various noise sources, it can be shown that PLL is uniquely suited for generation of stable,
low noise tunable RF signals for radio, timing and wireless applications.
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Madhu Kumar H R, Vishal Ramdurg, Rakesh Sukumaran, Design and Implementation of Low Power PLL in 0.18 CMOS Technology Using Custom Design Approach