ULTRA LOW POWER ROM ARCHITECTURE (IMPLEMENTATION OF MEMORY ARRAY)
| dc.contributor.author | MEGHA D R | |
| dc.contributor.author | RUKMINI N | |
| dc.date.accessioned | 2019-06-18T10:15:09Z | |
| dc.date.available | 2019-06-18T10:15:09Z | |
| dc.date.issued | 2019-06-18T10:15:09Z | |
| dc.description.abstract | Here we are designing the low power ROM architecture by implementing memory core which consumes less power when compared to conventional ROM architecture. This is achieved with help of many type of memory architecture of ROM such as NOR and NAND array and choosing best architecture for memory array. The low power ROM architecture is achieved by implementing selective precharge technique at architecture level. Large capacitance is switched during precharge cycle because all the bit lines are precharged high and many bit lines are discharged even when these locations are not accessed. By using selective precharge technique only the required bit line is precharged which reduces power consumption significantly. Selective precharge technique is implemented by designing an control block which helps in selecting a particular bit line which is to be precharged according to the required address accessing. Control block consist of decoder which consumes less power and less delay, by comparing different decoder we have chosen decoder using mixed logic which consist of both transmission gate logic and dual value logic. Simulation, layout and power analysis of different architecture is done using 180nm and 45nm technology in Cadence tool and spectra simulator. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/10497 | |
| dc.language.iso | en | en_US |
| dc.subject | 1NH15EC048 | en_US |
| dc.subject | 1NH15EC081 | en_US |
| dc.title | ULTRA LOW POWER ROM ARCHITECTURE (IMPLEMENTATION OF MEMORY ARRAY) | en_US |
| dc.type | Other | en_US |