Experimental Analysis And Design Of 1-D Median Filter Architecture With Rank Selection And Generation Process For Low Power Consumption
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2016-07-13T10:47:49Z
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Abstract
This brief is to design a low power median filter based on 2-stage pipelined
architecture where, word-level sorting of samples are used in the architecture in which the
samples are accepted sequentially in a FIFO manner and median output is generated at
each machine cycle. Ring architecture is used in this design with the help of token
registers to make the samples immobile to reduce the power consumptions. Performance
of the filter is shown by reducing the number of LUTs in the Rank Selection Module in
turn, where it reduces the delay, area, power consumption and increases the speed of
operation. Signal range is improvised to transmit more data in less time by reducing the
switching activities in the architecture by using the token registers in the ring format as
adopted in the design. Evaluated simulation results are showed in the analysis and
validated as per the design.
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Experimental Analysis And Design Of 1-D Median Filter Architecture With Rank Selection And Generation Process For Low Power Consumption, Arjun Ayagiri Tm