90nm Standard Library Cell Design Using GNU/Electric

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dc.contributor.authorKandati Praveen, Kumar
dc.contributor.authorHarish, P
dc.contributor.authorRigil, Gracious
dc.contributor.authorRohith, Prasad K M
dc.date.accessioned2018-06-27T11:21:19Z
dc.date.available2018-06-27T11:21:19Z
dc.date.issued2018-06-27T11:21:19Z
dc.description.abstractIn this project, we are designing a standard library cell with 90nm technology using GNU/Electric with MOCMOS technology. The library cell consists of 24 cells with each cell having the following views: Icon, Schematic and Layout. The standard library cell includes Basic Gates, Adder circuits, Flip-flops, Latches and Multiplexers. The parameters: Rise Time, Fall Time and Area for all these cells are calculated and listed in a table. Area of each cell in this library is compared with 180nm (CMOS Cells) and 300nm (MUDD Library) technologies. Simulation of each cell is done using LT-SPICE software. GDS file is generated for these cells and 3D view of the layouts is also shown.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/9612
dc.language.isoenen_US
dc.subjectKandati Praveen Kumaren_US
dc.subjectHarish Pen_US
dc.subjectRigil Graciousen_US
dc.subjectRohith Prasad K Men_US
dc.subject1NH14EC714en_US
dc.subject1NH14EC745en_US
dc.subject1NH14EC753en_US
dc.subject1NH14EC754en_US
dc.title90nm Standard Library Cell Design Using GNU/Electricen_US
dc.typeOtheren_US
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