Design and Implementation of RCA, CLA and CSA for Performance Optimization
| dc.contributor.author | Akhil, P | |
| dc.contributor.author | Neema, K | |
| dc.contributor.author | Rakesh, V | |
| dc.date.accessioned | 2016-07-13T04:28:43Z | |
| dc.date.available | 2016-07-13T04:28:43Z | |
| dc.date.issued | 2016-07-13T04:28:43Z | |
| dc.description.abstract | VLSI adders are critically important in digital designs since they are utilized in ALUs, memory addressing, cryptography, and floating-point units. Since adders are often responsible for setting the minimum clock cycle time in a processor, they can be critical to any improvements seen at the VLSI level. Adders are the main parts of processing circuits and play an important role in all mathematical operations like subtraction, multiplication, division, etc. Datapath units can’t build without using Adders but drawback of the existing adder architectures is the propagation delay. This propagation delay is due to the carry chain/path from the input to the output. The most important for measuring the quality of adder designs are computation time and area. Here different adder architectures are simulated and analyzed based on power dissipation, area and speed by using synopsis tool.Compare them qualitatively and quantitatively for circuit implementation . Ripple carry adder(RCA) is simple,but draw back is large delay. Carry Look ahead Adder (CLA) is one of the fastest adder structures where as carry select adder is best for its low area and delay. Based on the idea of above, Proposing the new architectures by optimizing the selected one, by combining of two architectures and sharing technique. The main aim of our work is to design and implement a Ripple carry adder Carry look ahead adder and Carry select adders using verilog and analyse the design parameters such as Area, Timing and Power. The circuit is designed and synthesized in TSMC 0.13μm CMOS technology and It is simulated using Synopsys VCS-MX.Area,timing and power metrices have been captured using Synopsys tools. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/6169 | |
| dc.language.iso | en | en_US |
| dc.subject | Design and Implementation of RCA, CLA and CSA for Performance Optimization | en_US |
| dc.subject | Rakesh | en_US |
| dc.subject | Akhil | en_US |
| dc.subject | Neema | en_US |
| dc.title | Design and Implementation of RCA, CLA and CSA for Performance Optimization | en_US |
| dc.type | Thesis | en_US |