PVT SCALING TECHNOLOGIES/METHODOLOGIES FOR 7nm FINFET TECHNOLOGY”
| dc.contributor.author | K.R.AMRUTHA | |
| dc.contributor.author | MONISHA.M | |
| dc.contributor.author | NAVEEN.K.R | |
| dc.contributor.author | SUBRAMANYA.G | |
| dc.date.accessioned | 2019-06-18T07:15:07Z | |
| dc.date.available | 2019-06-18T07:15:07Z | |
| dc.date.issued | 2019-06-18T07:15:07Z | |
| dc.description.abstract | Cell characterization is the process of simulating a standard cell with an analog simulator or an automated characterization tool to extract this information and convert into a format that other tools can utilize. Characterization requires adequate logic, timing, power consumption for each cell in the library. Cell characterization demands are increasing for following reasons With each technology node as each library is operated over multiple voltage domains driven by different application scenarios. The characterization is also an iterative process with a new node maturing over a period of time. Accounting On chip variation in the timing closure leads to requirement of AOCV/LVF characterization Because of above reasons over all cell library characterization is a very time/cost/cpu/license intensive process and handling a characterization process is a challenging job. Any effort in terms of cutting down on the PVT characterization will be huge problem solver for entire VLSI industry. Any commercial standard cell library needs to characterize 1500-2000 cells in each VT and channel length (typically 6-15 combinations) for over 50+ pvt corners. | en_US |
| dc.identifier.uri | http://hdl.handle.net/123456789/10484 | |
| dc.language.iso | en | en_US |
| dc.subject | 1NH15EC035 | en_US |
| dc.subject | 1NH15EC060 | en_US |
| dc.subject | 1NH15EC060 | en_US |
| dc.subject | 1NH15EC113 | en_US |
| dc.title | PVT SCALING TECHNOLOGIES/METHODOLOGIES FOR 7nm FINFET TECHNOLOGY” | en_US |
| dc.type | Other | en_US |