Design of a power efficient 16-bit posit multiplier and its application in image contrasting
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Date
2024
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Volume Title
Publisher
NHCE
Abstract
The ever-increasing demand for energy-efficient computing has driven the need for innovative approaches to arithmetic logic design. Traditional floating-point arithmetic units, including multipliers and Multiply-Accumulate (MAC) units, have long been essential for applications ranging from artificial intelligence and machine learning to image processing and scientific computation. However, these units are inherently power-hungry and require significant silicon area, which limits their suitability for modern systems that prioritize energy efficiency. Addressing these challenges, this project focuses on the design and implementation of a 16-bit posit multiplier. The posit number system, a promising alternative to IEEE-754 floating-point representation, offers a highly flexible structure that dynamically adjusts precision based on input data. This characteristic allows the posit architecture to achieve a superior trade-off between computational accuracy, power efficiency, and hardware area, making it an ideal candidate for next-generation arithmetic designs.