An Efficient High Speed Wallace Tree Multiplier

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dc.contributor.authorAdithya, Reddy M V
dc.contributor.authorArem Chenna, Keshav Reddy
dc.contributor.authorDinesh, M K
dc.date.accessioned2016-07-12T11:18:00Z
dc.date.available2016-07-12T11:18:00Z
dc.date.issued2016-07-12T11:18:00Z
dc.description.abstractWallace Tree Multiplication Algorithm has been implemented in four different ways to design an 8x8 multiplier viz., 1) Using 7:3 and 5:3 compressors 2) Using Dual-Weight 5:3 compressors 3) Using Full-adders and Half-adders 4) Using 5:3 compressors designed using two cascaded full adders. All the above mentioned multiplier circuits are compared with an 8x8 Braun Multiplier circuit. The performance of all the circuits has been analysed and compared using Cadence Encounter tool.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/6149
dc.language.isoenen_US
dc.subjectM K Dineshen_US
dc.subjectAdithya Reddy M Ven_US
dc.subjectArem Chenna Keshav Reddyen_US
dc.subjectAn Efficient High Speed Wallace Tree Multiplieren_US
dc.titleAn Efficient High Speed Wallace Tree Multiplieren_US
dc.typeThesisen_US
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