ULTRA LOW POWER ROM ARCHITECTURE -IMPLEMENT SENSING ARCHITECTURE

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dc.contributor.authorVENKATA RAMAKRISHNA M
dc.contributor.authorRADHIKA B
dc.contributor.authorA YAKSHIKA
dc.date.accessioned2019-06-14T08:11:31Z
dc.date.available2019-06-14T08:11:31Z
dc.date.issued2019-06-14T08:11:31Z
dc.description.abstractMoore’s law states that “The number of transistors doubles every eighteen months”, but today concepts such as “More than Moore”. As emerged the length of the channel for MOS device is reducing to 22nm and less, many problems are concerned with Power, Area and Speed. The VLSI design of non-volatile memories NOR-ROM has been carried out 180nm CMOS technology. The design of the schematics has been carried out using cadence CAD-tools. As the memory size increases, power consumption increases which becomes barrier for the battery life. So, low power VLSI plays a vital role in reduction of the power consumption. Here we have come up with selective per-charge and keeper circuit which helps in reduction of the power consumption.en_US
dc.identifier.urihttp://hdl.handle.net/123456789/10440
dc.language.isoenen_US
dc.subject1NH15EC047en_US
dc.subject1NH15EC078en_US
dc.subject1NH15EC129en_US
dc.titleULTRA LOW POWER ROM ARCHITECTURE -IMPLEMENT SENSING ARCHITECTUREen_US
dc.typeOtheren_US
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