Gate Level Simulation and Power Calculation of a Pcie Controller
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2016-07-12T10:57:28Z
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The increase in design sizes and the complexity of timing checks at 40nm technology nodes and below is responsible for longer run times, high memory requirements, and the need for a growing set of Gate-Level Simulation (GLS) applications including Design For Test (DFT) and low-power considerations. As a result, in order to complete the verification requirements on time, it becomes extremely important for GLS to be started as early in the design cycle as possible, and for the simulator to be run in high-performance mode. This application note describes new methodologies and simulator use models that increase GLS productivity, focusing on two techniques for GLS to make the verification process more effective. The impact of timing and power has become increasingly important as the geometries are shrinking. As the speeds of operation increases from 250MHz and crosses 500Mhz and reaches closer to 1GHz, the role of gate level simulation with SDF back annotation – also referred to as GLS simulation with timing delays becomes critical as we not only need to verify that the design got synthesized into a functionally correct netlist but also need to verify that the realized netlist post synthesis is functional and timing correct. Power is an important factor in today’s mobile and wearable computing era. Accurate power calculations are required to ensure that the system power intent is achieved. The power numbers calculated using gate level simulations are useful in achieving accurate power numbers. For IP providers, it is important that the power numbers shared with customers are as accurate as possible. Hence power calculation and analysis based on gate level simulation with SDF back-annotation is an important activity in the IP development process.
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Sanjana M, Sunitha N, Gate Level Simulation and Power Calculation of a Pcie Controller